1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of semiconductor devices, and, more specifically, to various methods of using a dual liner approach for forming CMOS integrated circuit products that employ FinFET devices, and the resulting device structures.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided on a restricted chip area. Transistors come in a variety of shapes and forms, e.g., planar transistors, FinFET transistors, nanowire devices, etc. A so-called metal oxide field effect transistor (MOSFETs or FETs) is one commonly employed circuit element that is found on integrated circuit products. The transistors are typically either NMOS (NFET) or PMOS (PFET) type devices wherein the “N” and “P” designation is based upon the type of dopants used to create the source/drain regions of the devices. So-called CMOS (Complementary Metal Oxide Semiconductor) technology or products refers to integrated circuit products that are manufactured using both NMOS and PMOS transistor devices. Irrespective of the physical configuration of the transistor device, each device comprises drain and source regions and a gate electrode structure positioned above and between the source/drain regions. Upon application of an appropriate control voltage to the gate electrode, a conductive channel region forms between the drain region and the source region.
A conventional FET is a planar device that typically includes a source region, a drain region and a channel region that is positioned between the source region and the drain region, and a gate electrode positioned above the channel region. To improve the operating speed of planar FETs, and to increase the density of planar FETs on an integrated circuit product, device designers have greatly reduced the physical size of planar FETs over the past decades. More specifically, the channel length of planar FETs has been significantly decreased, which has resulted in improving the switching speed and in lowering operation currents and voltages of planar FETs. However, decreasing the channel length of a planar FET also decreases the distance between the source region and the drain region. In some cases, this decrease in the separation between the source and the drain makes it difficult to efficiently inhibit the electrical potential of the source region and the channel from being adversely affected by the electrical potential of the drain. This is sometimes referred to as a so-called short channel effect, wherein the characteristic of the planar FET as an active switch is degraded.
In contrast to a planar FET, there are so-called 3D devices, such as an illustrative FinFET device, which is a three-dimensional structure. FIG. 1A is a perspective view of an illustrative prior art FinFET semiconductor device 10 that is formed above a semiconductor substrate 12. The simplistically depicted device 10 includes three illustrative fins 14, an isolation material 15, a gate structure 16, a sidewall spacer 18 and a gate cap layer 20. The gate structure 16 is typically comprised of a layer of insulating material (not separately shown), e.g., a layer of high-k insulating material, and one or more conductive material layers that serve as the gate electrode for the device 10. In this example, the fins 14 are comprised of a substrate fin portion 14A and an alternative fin material portion 14B. The substrate fin portion 14A may be made of silicon, i.e., the same material as the substrate, and the alternative fin material portion 14B may be made of a material other than the substrate material, for example, silicon-germanium. The fins 14 have a three dimensional configuration: a height H, a width W and an axial length L. The axial length L corresponds to the direction of current travel in the device 10 when it is operational, i.e., the gate-length direction. The portions of the fins 14 covered by the gate structure 16 are the channel regions of the FinFET device 10. In a conventional process flow, the portions of the fins 14 that are positioned outside of the spacers 18, i.e., in the source/drain regions of the device 10, may be increased in size or even merged together (not shown in FIG. 1A) by performing one or more epitaxial growth processes. The process of adding epi material on the portions of the fins 14 in the source/drain regions of the device 10 is performed to reduce the resistance of source/drain regions and/or make it easier to establish electrical contact to the source/drain regions.
Unlike a planar FET, in a FinFET device, a channel is formed perpendicular to a surface of the semiconducting substrate so as to increase the drive current per footprint of the device. Also, in a FinFET, the improved gate control through multiple gates on a narrow, fully-depleted semiconductor fin significantly reduces the short channel effects. When an appropriate voltage is applied to the gate electrode of a FinFET device, the surfaces (and the inner portion near the surface) of the fins 14, i.e., the vertically oriented sidewalls and the top upper surface of the fin (for a tri-gate device), form a surface inversion layer or a volume inversion layer that contributes to current conduction. In a FinFET device with a single fin, the “channel-width” is estimated to be about two times (2×) the vertical fin-height plus the width of the top surface of the fin, i.e., the fin width. Multiple fins can be formed in the same foot-print as that of a planar transistor device. Accordingly, for a given plot space (or foot-print), FinFETs tend to be able to generate significantly higher drive current than planar transistor devices. Additionally, the leakage current of FinFET devices after the device is turned “OFF” is significantly reduced as compared to the leakage current of planar FETs, due to the superior gate electrostatic control of the “fin” channel on FinFET devices. In short, the 3D structure of a FinFET device is a superior MOSFET structure as compared to that of a planar FET, especially in the 20 nm CMOS technology node and beyond.
Device manufacturers are under constant pressure to produce integrated circuit products with increased performance and lower production costs relative to previous device generations. Thus, device designers spend a great amount of time and effort to maximize device performance while seeking ways to reduce manufacturing costs and improve manufacturing reliability. As it relates to 3D devices, device designers have spent many years and employed a variety of techniques in an effort to improve the performance, capability and reliability of such devices. Device designers are currently investigating using alternative semiconductor materials, such as so-called SiGe, Ge and III-V materials, to manufacture FinFET devices which are intended to enhance the performance capabilities of such devices, e.g., to enable low-voltage operation without degrading their operating speed. FIGS. 1B-1E depict one illustrative problem that may be encountered when forming FinFET devices comprised of alternative fin material.
FIG. 1B depicts an illustrative FinFET 30 at a point in fabrication where several process operations have been performed. More specifically, a layer of alternative semiconductor material 38 (e.g., SiGe or Ge) was initially formed on the substrate 12, and a patterned masking layer 32 was formed above the alternative semiconductor material 38. Thereafter, one or more etching processes were performed through the patterned masking layer 32 to form a plurality of fin-formation trenches 34 that extend into the substrate 12. These process operations result in the definition of five illustrative fins comprised of a substrate fin portion 36 and an alternative material portion 38. Next, a thin liner layer 40 (e.g., silicon nitride) was formed on the fins and in the trenches 34 by performing a conformal deposition process, e.g., atomic layer deposition (ALD) or chemical vapor deposition (CVD). Next, a layer of insulating material 42 (e.g., silicon dioxide) was blanket-deposited so as to overfill the trenches 34.
FIG. 1C depicts the device 30 after a chemical mechanical planarization (CMP) process was performed that stops on the patterned masking layer 32. FIG. 1D depicts the device 30 after a recess etching process (i.e., a so-called “fin reveal” etching process) was performed to recess the layer of insulating material 42 to a desired level such that the desired amount of the fin, i.e., the alternative material portion 38, is exposed.
FIG. 1E depicts the device 30 after an etching or cleaning process was performed to clear the exposed fin of the silicon nitride liner 40 and the patterned masking layer 32. Any remnants of silicon dioxide that may be present on the fin at this time (e.g., a pad oxide) may also be removed at this point in time. Unfortunately, the alternative fin material 38 may also be attacked during these etching/cleaning process operations and portions of the alternative fin material 38 may be undesirably consumed during these process operations, as reflected by the reduced-size alternative fin material 38R shown in FIG. 1E. Such undesirable consumption may adversely impact device performance characteristics.
The present disclosure is directed to various methods of using a dual liner approach for forming CMOS integrated circuit products that employ FinFET devices, and the resulting device structures, that may solve or reduce one or more of the problems identified above.